the present invention relates to integrated circuit devices and, more particularly, to multi-phase clock generators.
Integrated circuit chips typically utilize externally generated clock signals to generate on-chip clock signals that are utilized at the chop level and system level to achieve accurate synchronization of devices therein. These externally generated clock signal over a system board containing one or more interconnected chips that may need to communicate with each other in synchronization. The waveform of an externally generated clock signal typically cannot be used as an on-chip clock signal because only a single phase is typically available, its duty cycle typically cannot match the requirements of the chip logic and buffering is needed to drive large loads. According, on-chip clock generators are frequently provided to generate one or more internal clock signals having a high degree of synchronization with each other. Examples of techniques to synchronize clock signals at the chop and system level are more fully described at section 9.5 of a textbook by J. M. Rabaey, entitled Digital Integrated Circuits: A Design Perspective, Prentice-Hall, Inc., ISBN 0-13-178609-1, pp. 538-543 (1996).
On-chip clock generators may perform a divide-by-two function when generating a pair of internal clock signals and a divide-by-four function when generating two pairs of internal clock signals. One example of a divide-by-two clock generator is described in U.S. Pat. No. 5,249,214 to Ulmer et al., entitled xe2x80x9cLow Skew CMOS Clock Divider.xe2x80x9d Another example of a divide-by-two clock generator is described in U.S. Pat. No. 6,049,236 to Walden, entitled xe2x80x9cDivide-by-One or Divide-by-Two Qualified Clock Driver with Glitch-Free Transitions.xe2x80x9d Examples of conventional onchip clock generators that perform a divide-by-four function are illustrated by FIGS. 1A-1B.
In FIG. 1A, a plurality of identical D-type flip flops are utilized to generate a first pair of clock signals CLK2_R and CLK2_F in response to an external clock signal CLK. This first pair of clock signals have a frequency equal to one-half a frequency of the external clock signal CLK, with signals CLK2_R and CLK2_F being triggered on rising and falling edges of the external clock signal CLK, respectively. The clock generator of FIG. 1A also generates second and third pairs of clock signals (CLK4_0R, CLK4_2F) and (CLK4_1R, CLK4_3F), having frequencies that are equal to one-quarter a frequency of the external clock signal CLK. These divide-by-two and divide-by-four functions are achieved by feeding back the complementary output QB of each D-type flip-flop to its respective input (D). A reset feature is provided by an active low reset signal RESETB.
The clock generator of FIG. 1B is similar to the clock generator of FIG. 1A, however, the clock generator of FIG. 1B utilizes three D-type flip flops having complementary outputs (Q and QB) and three D-type flip flops having only single true outputs (Q). As illustrated, each complementary output QB of a flip flop is fed back to its respective input and every true output Q of the flip flops having dual outputs is connected to a data input of a respective flip flop having only a single output, as illustrated. Unfortunately, the clock generators of FIGS. 1A-1B may have unnecessarily long setup and hold times if the dynamic switching performance of each D-type flip flop is not sufficiently uniform and fast. For example, a full low-to-high or high-to-low signal swing is needed at each data input (D) of each D-type flip flop before it can be latched by the respective clock signal.
Multi-phase clock generators having improved setup and hold time characteristics according to a first embodiment of the present invention include a master-slave flip flop that generates a second pair of clock signals having a second frequency in response to a first pair of clock signals having a first frequency greater than the second frequency. The master-slave flip-flop includes a master stage that is responsive to a first one of the first pair of clock signals and has a first pair of differential inputs and a first pair of differential outputs. A slave stage is also provided. The slave stage is responsive to a second one of the first pair of clock signals and has a second pair of differential inputs coupled to the first pair of differential outputs and a second pair of differential outputs that are cross-coupled and fed back to the first pair of differential inputs of the master stage.
The first pair of clock signals are preferably a first pair of complementary clock signals, with the master stage including a master differential amplifier circuit that is responsive to a true one of the first pair of complementary clock signals and a master pair of cross-coupled logic gates having inputs electrically coupled to differential outputs of the master differential amplifier circuit. These cross-coupled logic gates may constitute two-input NAND gates. The master stage may also include an equalization circuit that is responsive to the true one of the first pair of complementary clock signals and is electrically coupled across the differential outputs of the master differential amplifier circuit. A precharge circuit is also provided. The precharge circuit is also responsive to the true one of the first pair of complementary clock signals and may include a pair of PMOS pull-up transistors electrically coupled to the differential outputs of the master differential amplifier circuit. Because the first pair of differential inputs associated with the master stage, which are cross-coupled to the second pair of differential outputs of the slave stage, typically require only about 100 mV differential voltage prior to a leading edge of the true one of the first pair of complementary clock signals, reduced setup times can be achieved. Reduced hold times may also be simultaneously achieved by reducing the loading on the inputs and outputs of the cross-coupled logic gates.
According to still further aspects of this embodiment, the slave stage preferably includes a slave differential amplifier circuit that is responsive to a complementary one of the first pair of complementary clock signals. The slave stage also includes a slave pair of cross-coupled logic gates having inputs electrically coupled to differential outputs of the slave differential amplifier circuit.
A multi-phase clock generator according to another embodiment of the present invention may include a complementary clock generator that generates true and complementary clock signals that are about 180xc2x0 out-of-phase relative to each other. A master latched sense amplifier and a slave latched sense amplifier are also provided. The master latched sense amplifier is responsive to the true clock signal and has a first pair of differential inputs and a first pair of latched differential outputs. The slave latched sense amplifier is responsive to the complementary clock signal and has a second pair of differential inputs electrically coupled to the first pair of latched differential outputs and a second pair of latched differential outputs electrically cross-coupled and fed back to the first pair of differential inputs.
According to still another embodiment of the present invention, a divide-by-four clock generator having excellent setup and hold time characteristics includes a first divide-by-two clock generator that is responsive to a primary clock signal. The first divide-by-two clock generator includes a master latched sense amplifier and a slave latched sense amplifier. The master latched sense amplifier includes a first pair of differential inputs and a first pair of latched differential outputs. The slave latched sense amplifier has a second pair of differential inputs electrically coupled to the first pair of latched differential outputs and a second pair of latched differential outputs that are electrically cross-coupled and fed back to the first pair of differential inputs of the master latched sense amplifier. Second and third divide-by-two clock generators are also provided. The second divide-by-two clock generator has a clock input electrically coupled to one of the first pair of latched differential outputs generated by the master latched sense amplifier within the first divide-by-two clock generator. The third divide-by-two clock generator has a clock input electrically coupled to one of the second pair of latched differential outputs -generated by the slave latched sense amplifier within the first divide-by-two clock generator. The second and third divide-by-two clock generators may be similar in construction to the first divide-by-two clock generator.
According to a preferred aspect of this embodiment, the clock input of the second divide-by-two clock generator is electrically coupled to a complementary one of the first pair of latched differential outputs generated by the master latched sense amplifier within the first divide-by-two clock generator. In addition, the clock input of the third divide-by-two clock generator is electrically coupled to a true one of the second pair of latched differential outputs. To provide a preferred reset feature independent of the state of the primary clock signal, first and second MOS transistors may be provided within the first divide-by-two clock generator. The first MOS transistor may have a first current carrying terminal electrically connected to a true one of the first pair of latched differential outputs and a gate responsive to a reset signal. The second MOS transistor may have a first current carrying terminal electrically connected to the true one of the second pair of latched differential outputs and a gate responsive to the reset signal. These MOS transistors may comprise NMOS pull-down transistors. The second and third divide-by-two clock generators may have similar reset circuitry.